Working with RISC-V

As of a few months ago I started gaining interest development using the fairly new RISC-V platform. I started writing emulators using the Zig, learning the ins-and-outs of it such as how instructions are encoded, what registers there are, anything required to basically get a simple emulator that could run an operating system as basic as xv6. As of recently I took this up a notch by moving from writing emulators to now currently writing a kernel that can run on the RISCV64 architecture. I currently have a repository that you can see here which contains the barebones boilerplate to boot, trap (which at the moment is just a mret instruction), as well as call into a Zig function as your kernel source.

Recently I discovered the microgrant program. Which was created by Parker Hendo on twitter, you can see his profile here, as well as a few friends and some companies/volunteers who donated money to provide small grants for people with interesting projects. I applied not expecting at all that I would be approved for one, however I was and I couldn’t be more thankful. I was given $300 in funds to use for anything I want in regards to my projects and research in relation to RISC-V.

In the future I hope to be able to contribute to the RISC-V backend for the Zig compiler, but as it is currently I am no where near knowledgable enough to try to attempt a task like this. The x86 architecture is extremely complicated, an example of this is this paper which states the following:

Based on the breakout in Table 1, culled from the intel instruction set reference, we add up 822 instruction mnemonics. But Heule et. al. states that the current x86-64 design “contains 981 unique mnemonics and a total of 3,684 instruction variants” [2]. However they do not specify which features are included in their count.

Let this sink in, the x86 architecture contains over 3000 instruction variants. That is a lot of instructions and probably extremely inefficient at that, this is horrible, let alone I can’t even seem to find a concrete source for the amount of ARM instructions, as there is many different variations of the ISA. Compared to x86 and ARM, RISC-V is a lot simpler and efficient in terms of the amount of instructions it uses and needs, the base RV32I instruction set only has 47 instructions as stated here. The RV32I ISA is the only required instruction set for a RISC-V chip to function in theory, however most manufacturers and OEM providers will also implement the RV64I ISA among others for the best support in a lot of cases.

These things aside, I recently ordered a RISC-V development board so I can test things on real hardware, the board in question specifically is the HiFive Rev B. I wanted the HiFive Unmatched however it seems to either be sold out, not out yet, or not being given to consumers. None the less, being able to test my kernel, among other things on actual RISC-V hardware will significantly allow me expand my knowledge and debug capabilities when it comes with working with the architecture.

The SiFive boards including the one I ordered comes with it’s own software based on the Eclipse IDE, known as Freedom Studio. While I may be using this for some things, in most cases I will be using other things as I will mostly be testing low level things that the SDK and IDE can not really help with.

Big thanks to the people over at! A list of most of the projects and their maintainers has been posted on twitter and can be seen here. They have mentioned the possibility of making a Slack or Discord where people can share projects they are working on, regardless if they received a grant or not. I look forward to meeting other people and seeing their amazing projects, and of course working on my own.